Cache Memory and Pipelining Questions

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13.

Whenever the data is found in the cache memory it is called as _________

A

HIT

B

MISS

C

FOUND

D

ERROR

Correct Answer: A

Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.

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14.

LRU stands for ___________

A

Low Rate Usage

B

Least Rate Usage

C

Least Recently Used

D

Low Required Usage

Correct Answer: C

LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.

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15.

When the data at a location in cache is different from the data located in the main memory, the cache is called _____________

A

Unique

B

Inconsistent

C

Variable

D

Fault

Correct Answer: B

The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.

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16.

Which of the following is not a write policy to avoid Cache Coherence?

A

Write through

B

Write within

C

Write back

D

Buffered write

Correct Answer: B

There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.

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17.

Which of the following is an efficient method of cache updating?

A

Snoopy writes

B

Write through

C

Write within

D

Buffered write

Correct Answer: A

Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.

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18.

In ____________ mapping, the data can be mapped anywhere in the Cache Memory.

A

Associative

B

Direct

C

Set Associative

D

Indirect

Correct Answer: A

This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.

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19.

The number of sign bits in a 32-bit IEEE format is ____

A

1

B

11

C

9

D

23

Correct Answer: A

There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

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20.

The transfer between CPU and Cache is ______________

A

Block transfer

B

Word transfer

C

Set transfer

D

Associative transfer

Correct Answer: B

The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.

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